1. Field of the Invention
This invention relates to a method of producing a semiconductor device. Particularly, it relates to a method whereby, when a region which requires high-temperature heating and a region which should avoid high-temperature heating are intermingled on the same substrate, sufficient thermal treatment can be performed to the former region without having adverse effects on the latter region.
2. Description of the Prior Art
In a manufacture process of a semiconductor device, various kinds of anneal processing (heat treatment) are performed.
For example, in case of forming source/drain regions of an MOS-FET, activation annealing is performed in order to recover crystallinity of a semiconductor substrate disordered by ion implantation, and to electrically activate implanted acceptor ions and donor ions.
Moreover, in a process of silicidation of the surface layer portion of the source/drain regions for reducing contact resistance of MOS-FET, silicidation annealing is performed in a high-temperature range in order to form a silicide layer by a reaction of so-called high fusion point metals, such as W, Mo, and Ti, or precious metals of comparatively high fusion point, such as Pt and Pd, with an Si substrate.
As the method of such annealing, furnace annealing using an electric furnace, rapid thermal annealing (RTA) using an infrared lamp, and laser annealing using a laser light source are conventionally known.
Meanwhile, as large-scale integration of the device proceeds, it becomes necessary to reduce the depth of an impurity diffused region in the source/drain regions, that is, a junction depth, in each MOS-FET. In this case, if activation annealing or silicidation annealing is carried out by furnace annealing or RTA, there is a problem that temperature-rising speed and temperature-falling speed of a substrate become low, thus increasing the junction depth. On the contrary, in laser annealing, one shot of a laser pulse is as short as of the order of picosecond to nanosecond, and the energy of the laser pulse is absorbed mostly within a shallow range of about 20 nm from the surface of an irradiated layer. Thus, the surface of the semiconductor substrate is heated close to the fusion point, and a region to the depth of about 100 nm can be activated. For this reason, laser annealing is highly suitable for activation of the source/drain regions, and particularly for activation of a low-concentration impurity diffused region of LDD (Lightly Doped Drain) structure.
Meanwhile, at the time of activation or silicidation of the source/drain regions of the MOS-FET, it is normal that a gate electrode is already formed. Particularly in a highly integrated semiconductor device, it is often the case that many electrode patterns and metallization patterns of other devices are already formed. Accordingly, at the time of laser annealing, these patterns are heated concurrently. However, a problem has arisen that the patterns are deformed by the heating in connection with a reduction in the design rule.
The electrode pattern and the metallization pattern of the semiconductor device are usually formed on a dielectric film. For example, thermal conductivity (0.014W/cm.deg) of SiO.sub.2, which is a typical dielectric, is lower than thermal conductivity (1.5 W/cm.deg) of an Si substrate. For this reason, heat storage proceeds inside the pattern on the SiO.sub.2 film, whereby the heat deforms the pattern.
For solving this problem, it is conceivable to control the heat storage in the electrode pattern or the metallization pattern by reducing the laser power. However, with this method, the rate of activation of ions in the LDD region is lowered, thus easily generating adverse effects such as a reduction in operating speed of the MOS-FET due to an increase in resistance, an increase in leakage current due to failure to sufficiently recover crystallinity of the semiconductor substrate, and failure to attain a desired reduction in contact resistance due to insufficient proceeding of silicidation.
For example, a relation between junction depth and sheet resistance in the case of performing XeCl excimer laser annealing (ELA, wavelength of 308 nm) to an Si substrate into which ion implantation of impurities is carried out as shown in FIGS. 1, 2 and 3. The horizontal axis in FIG. 1 indicates a p.sup.+ n junction depth (nm) of a p.sup.+ -type source/drain regions formed by ion implantation of BF.sub.2.sup.+ into an n-type Si substrate. The horizontal axis in FIG. 2 indicates an n.sup.+ p junction depth (nm) of an n.sup.+ -type source/drain regions formed by ion implantation of As.sup.+ into a p-type Si substrate. The vertical axes in both FIGS. 1 and 2 express sheet resistance (.OMEGA./ ). The ion implantation is carried out via a gate SiO.sub.2 film with a thickness of 10 nm, under conditions of implantation such as an ion acceleration energy of 15 keV and a dose amount of 3.times.10.sup.15 /cm.sup.2. Moreover laser annealing is carried out via a reflection control SiO.sub.2 film with a thickness of 50 nm. The optical energy density at this time (mJ/cm.sup.2) is mentioned by the side of a plot.
FIG. 3 shows characteristics of n-MOS-FET which is formed under the conditions of FIG. 2 with different energy density of ELA and which has a channel length of 0.3 .mu.m and a channel width of 2 .mu.m. FIG. 3a shows the characteristics of the sample annealed at 0.7 J/cm.sup.2. Poor characteristics of a high leakage current at reverse bias and a low drain current are indicated. It is considered that the energy of ELA is not sufficient to anneal the electrical defects and impurities. A fairly low leakage current and a steep sub-threshold slope with a sufficient drain current are obtained as shown in FIG. 3b. The improved characteristics are considered to be caused by a decrease in electrical defects and sheet resistance due to a high energy irradiation of 0.9 J/cm.sup.2.
It is clear that an optical energy density up to about 1100 mJ/cm.sup.2 can be used, in order to anneal the source/drain regions sufficiently and to set the junction depth to not more than 100 nm. Actually, however, if the optical energy density exceeds 800 mJ/cm.sup.2, the electrode pattern and the metallization pattern are very likely to be deformed. Moreover, if the optical energy is too small, the sheet resistance increases sharply.
It is also conceivable, as another countermeasure to the problem, to change the energy density of the laser in accordance with characteristics of an irradiated portion. However, this countermeasure cannot avoid a drastic reduction in throughput, and thus is not practical.
Thus, it is an object of the present invention to provide a method of producing a semiconductor device whereby deformation of a gate electrode or a metallization pattern can be prevented while a shallow junction of low resistance is formed in a minute MOS-FET.